Job Description

Post Silicon Validation Engineer

Location: Santa Clara, CA

Schedule: Onsite, 5 days/week

Job Overview

Seeking a hands-on Post Silicon Validation Engineer to support system bring-up, power/performance measurements, interface validation, and hardware–software co-validation. The role involves extensive lab work, debugging, and electrical measurements across a range of hardware interfaces.

Key Responsibilities

• Perform power & performance measurements and analyze results.
• Support DDR interface bring-up, testing, and qualification.
• Conduct PVT (Process, Voltage, Temperature) validation for system stability.
• Perform electrical measurements on IO interfaces and execute first-level debug.
• Validate functional behavior of IO interfaces across use cases.

Requirements

• BE/BTech with 1–6 years of experience.
• Strong fundamentals in digital design and signal integrity.
• Ability to interpret schematics, PCB files, and voltage regulator basics.
• Good understanding of PC architecture and modern hardware–software interactions (BIOS/Driver/OS).
• Lab experience with DSO, multimeters, power supplies, and understanding of equipment specifications.
• Scripting knowledge (Perl/Python).
• Proficient in Windows, Linux, and MS Office tools.
• Strong analytical and problem-solving skills.

Preferred Skills

• Silicon characterization exposure.
• Board bring-up and testing experience.
• Knowledge of DDR and SERDES interfaces.
• Familiarity with tools such as BERT, protocol analyzers, logic analyzers, DMM/DAQ.

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